1. Field of the Invention
The present invention relates to a controller which controls an operation of a nonvolatile semiconductor memory device and a semiconductor memory system including a nonvolatile semiconductor memory and a controller therefore, for example, a controller which controls an operation of a flash memory device and a semiconductor memory system including a flash memory and a controller therefore.
2. Description of the Related Art
An example of a conventional operation for a semiconductor memory system including a semiconductor memory device, such as flash memory and a controller which controls the flash memory will be described below. This semiconductor memory system is connectable to a host device or soldered on a circuit board of the host device. The host apparatus transmits a command and data to the semiconductor memory device and exchanges data with the semiconductor memory device. As the host apparatus, for example, mobile electronic devices such as a digital camera, a mobile phone, and a personal computer are known.
When the host apparatus issues a command to the controller, the command is temporarily stored in a command latch circuit in the controller. Subsequently, a CPU (central processing unit) in the controller reads the command to set a sequence required to access the flash memory in a plurality of registers in the controller. Furthermore, the CPU sets valid bit registers corresponding to the plurality of registers and sets the in-use/not-in-use of a data RAM in the controller.
Upon completion of all the settings, a direct memory access (to be referred to as DMA hereinafter) start is executed, and access to the flash memory is started. At the end of the access, the CPU is notified of the end of access. Subsequently, when the flash memory is accessed, the plurality of registers and the valid bit registers are reset. Upon completion of setting of all the registers, the DMA start is executed, and the next access to the flash memory is started. The DMA means a process in which an apparatus such as the host apparatus and the memory device directly exchange data without using the CPU.
Upon completion of the sequence required for the flash memory, the CPU returns a ready signal to the host apparatus side, and is set in a standby state to wait for an input of a next command. Thereafter, when the next command is issued from the host apparatus, the controller repeats the same operation as described above.
In the conventional method described above, the CPU must set the registers in accordance with various command sequences to be issued to the flash memory. In response to one command request from the host apparatus, an access to the flash memory frequently requires a plurality of sequences. Each time the flash memory is accessed, the CPU requires a time to set the registers. As a result, an occupancy time of the CPU is dominant, and access performance to the flash memory becomes poor, disadvantageously. In particular, a time from when the host apparatus begins to access the controller, that is, when a command is input to the controller to when an access to the flash memory is actually ended becomes long, disadvantageously. FIG. 7D shows access times of parts in a conventional semiconductor memory device.
For example, Jpn. Pat. Appln. KOKAI Publication No. 2003-141888 discloses a nonvolatile semiconductor memory device including a plurality of registers which set pieces of information required to access a memory cell array and a sequencer which accesses the memory cell array on the basis of the information set in the registers.